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Data Flow
ChipWrights’ Innovative Approach Optimizes SoC Internal Dataflow

January 29, 2009

Bedford, MA, January 29, 2009. ChipWrights, Inc. - part of AD Group – Cary Robins, President of ChipWrights and SoC technology expert, highlighted ChipWrights’ innovative approach to solving dataflow issues common in traditional SoC technology when he spoke at the IP Based Electronic System Conference and Exhibition (IP 08).

Robins discussed ChipWrights’ hybrid approach to solving the performance-related problems resulting from high bandwidth Intellectual Property (IP) integration into SoC design. He noted that in traditional SoC design, the task of inter-IP communication has often been inadequate. A popular solution was to implement the AHB bus architecture as the IP interface standard, but as the complexity of SoCs increased the AHB bus architecture alone proved to be an insufficient solution.

ChipWrights’ SoC design uses both the AHB bus for control path operations and point-to-point Basic Virtual Component Interface (BVCI) connections through an internal crossbar for data flow. “This combination solves the performance-related issues that plague traditional SoC designs, such as high-latency, power consumption and simultaneous data transfers,” said Robins, President of the Bedford, Massachusetts-based Semiconductor Company.

In addition, the system is implemented with three connection fabrics: they support the three target devices being arbitrated for: External DRAM, Internal SRAM, and Control and Status Registers (CSR). This optimization allows concurrent accesses to the SRAM, DRAM and to the register space.

The AHB bus works nicely in this case. Since the CSRs are low speed devices that move little or no data, the total bandwidth required is easily handled. The AHB bus also maintains multi-master generality that the ChipWrights design requires. Since the clock frequency on the AHB implementation can be slow, Robins noted that the metal delay and power problems associated with the AHB bus are a non-issue, as is the worst case latency problems as high-speed data is not being moved on the bus.

The connection fabric for each memory element consists of a crossbar with low overhead point-to-point links from each master device (processor or DMA) using the BVCI standard. A major advantage of BVCI is its “fire and forget” capability, said Robins. The outgoing read request transaction is decoupled from the return data transaction. Outgoing read transactions are released in one clock cycle and (since they only contain an address) they pass through the switch in one cycle. Outgoing Write transactions take one cycle for address and one cycle for each data word in the burst and are released with a local handshake acknowledgment, but without an acknowledge extending back from the memory write operation. The outgoing read and write transactions can be interleaved and pipelined as deeply as necessary. Read data is returned on a distinct return path in the order the Read operations were issued. The pipelining affects read latency, but not system performance.

“For crossbar arbitration, the better conceived your arbitration mechanism, the closer to full utilization you can achieve,” said Robins. ChipWrights uses a small programmable table that provides options for the best-suited arbitration method at the time: static fixed priority, programmable fixed priority, round-robin priority, and weighted round-robin priority.

ChipWrights’ design “removes all artificial internal bandwidth bottlenecks and limits performance only by the processing and inherent memory bandwidth limitations,” concluded Robins. For more information, read the Optimizing SoC Internal Dataflow Using Standard Interfaces white paper.

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