5 megapixel camera - turnkey solution

CW5521 System-on-Chip Specification Table

System-on-Chip Components
CWv16 SIMD DSP Engine
  • Serial RISC control processor; 16 parallel vector processing units
  • 19,200 MMACs (maximum)
  • Very Dense Instruction Word (VDIW) technology - Provides benefit of VLIW in a 32-bit instruction
  • Sub-word parallelism allows multiple operands in packed data formats
  • Vector processor units can access their processor units simultaneously
  • Thirty-one 32-bit registers per vector processor
  • One 96-bit accumulator per vector processor
Instructions to accelerate image processing
  • Parallel memory access for packed data types
  • Logical serial shift operators
  • Inverted parallel branching
  • Post-iteration incrementing for serial loops
  • 4-bit multiplication improvements
  • Enhanced debugging capability
Special instructions to accelerate image processing
  • Operate on packed byte and word data types
  • Strided and table memory access
  • Sum of absolute differences for motion estimation calculations Dot product for color space conversion
  • Saturate operators for clamping
Embedded Data Memory
  • 256 KB
Extensive instruction cache
  • 16 KB direct mapped cache holds 4,096 thirty-two bit instructions
  • 64-byte block size with lock capability
External memory interface
  • 32-bit DDR-SDRAM interface
  • 256 MB (maximum)
  • Write FIFO to increase system bus performance
  • Speculative pre-fetch buffers to reduce average read latency
Independent DMA channels (8)
  • Embedded to external memory/external to embedded memory
  • Video input to memory/Memory to video output
  • USB to memory/memory to USB
  • SD to memory/memory to SD
  • JPEG encoder to memory/memory to JPEG encoder
AHB system bus
  • Dual 32-bit internal high speed
JPEG encoder
  • Dedicated hardware encoder with associated direct memory access
Parallel/Video input port
  • 8 or 16-bit configurable input
  • Sync pulse generation for CCD/CMOS image sensor interface
Parallel/Video output port
  • 8-bit or 16-bit configurable output
  • Sync pulse generation for driving digital display
  • Three 10-bit DACs for driving analog displays
  • Support for CVBS, RGB555, RGB565, and RGB545
Host/Peripheral interface
  • Connects to off-chip peripherals, such as boot ROM, when acting as system host processor
  • Connects to host processor when acting as co-processor
  • CompactFlash and ATA/ATAPI device support
Audio CODEC interface
  • Interfaces to I2S audio devices
  • 2.0 HS (480 Mbps maximum)
Dual SSI
  • Supports SPI and Microwire™ protocols
UART port
  • 16550 compatible
147 GPIO pins
  • 48 dedicated
  • 99 multiplexed
  • 4 programmable 32-bit timers/counters
  • 1 watchdog timer
PWM interface
  • 3 Stepper motor controls
IEEE-1149.1 compatible JTAG interface
  • Supports boundary SCAN
  • Allows real time debugging within ChipWrights development environment
Ball grid array
  • 496-pin package
  • 0.65 mm ball pitch
0.13 um technology  
  • Voltage
  • 1.0-1.1V core (variable [determines best performance and power settings for application])
  • 3.3V IO
  • 2.5V DDR-SDRAM
Power consumption
  • Less than 1 W typical power consumption at 1.1V
System-on-Chip Performance
MMACS 19,200 (maximum)
Maximum DSP Clock Frequency 300 MHz
Primary Memory 256 KB
External Memory 32-bit DDR-SDRAM
Instruction Cache 16 KB
Parallel Input Interface 8-bit,16-bit, or 32-bit digital
Parallel Output Interface 8-bit or 16-bit digital, 3x10-bit DAC
Timer Modules 4 programmable, 1 watchdog
Host/Slave Support 8- or 16-bit asynchronous, 8 chip selects
DMA Channels 8
Removable Storage CompactFlash®, SecureDigital
USB 1.1
Core Voltage 1.6V
IO Voltage 3.3V
DDR Voltage 2.5V
Package 256-pin BGA (1.0mm ball pitch)


CW5521 System on Chip